Integrated circuit including fully testable small scale read only memory constructed of level sensitive scan device shift register latches
US5694346A · kind A · utility
3Cited by
10References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1996 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Aug 21, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N17/004
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an integrated microprocessor chip. The chip includes a digital video decoder Inverse Discrete Cosine Transform element and an on chip Read Only Memory. The on chip Read Only Memory includes (a) a shift register latch for receiving data from off chip pull-up resistors, (b) a register for storing data, (c) a selector and a decoder for selecting memory cells to be read from the register, and (d) a Read Only Memory data output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.