Reading circuit for memory cell devices having a low supply voltage
US5694363A · kind A · utility
14Cited by
18References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 1996 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Apr 25, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for reading memory cells, wherein the device contains two branches, wherein each branch comprises, connected in cascade, an electronic switch, an active element reactively connected to the active element of the other branch, so as to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element. A microswitch connects the two branches together is inserted between the two active elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.