Semiconductor memory device capable of setting the magnitude of substrate voltage in accordance with the mode
US5694365A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 1997 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Jan 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM includes a substrate voltage generation unit for generating a substrate voltage having a negative value to be applied to a first node. The substrate voltage generation unit includes a detecting circuit. The detecting circuit includes a first PMOS transistor provided in series between a second node with a ground potential and a third node and a second PMOS transistor, and further includes a third PMOS transistor provided in parallel to the first PMOS transistor. The first and second PMOS transistors have the gates connected to the third node, and the third PMOS transistor has a gate receiving a signal. The detecting circuit is provided between the second node with the ground voltage and the first node, and further includes an NMOS transistor having a gate connected to the third node. The third PMOS transistor receives the signal of the "L" level in the self refresh mode and the signal of the "H" level in the normal mode. As a result, the clamp level of the substrate voltage is greater in the self refresh mode than in the normal mode. More specially, the NMOS transistor is turned on with the greater substrate voltage in the self refresh mode than the normal mode, so that the s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.