Automated design analysis system for generating circuit schematics from high magnification images of an integrated circuit
US5694481A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1995 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Apr 12, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V30/422
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of analyzing at least a portion of an integrated circuit (IC) comprised of the steps of automatically: (a) scanning at least a portion of a layer of an integrated circuit using high magnification to provide first digital signals representing pixel amplitudes, (b) extracting features of interest from the first digital signals to provide second digital signals representing values of groups of pixels defining the features of interest, (c) modifying the second digital signals representing adjacent features of interest from step (b) so as to mosaic the features of interest and providing third signals representing a seamless representation of the layer, (d) repeating steps (a), (b) and (c) for other layers of the integrated circuit, whereby plural third signals representing plural ones of the layers are provided, (e) registering the plural third signals relative to each other so as to represent vertical alignment of the layers by determining features of interest representative of IC mutual interconnection locations between layers, and using the locations as control points for the registering, and establishing an integrated circuit layout database therefrom, (f) generating a netl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.