Time multiplexing address and data on an existing PC parallel port
US5694557A · kind A · utility
8Cited by
5References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1994 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Aug 10, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4269
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of communicating with peripheral devices via a personal computer parallel port having computer data bus lines but no address bus lines comprising connecting the input of a multiplexer to the parallel port, the multiplexer having a data bus input and a databus output and an address bus output, applying address data to the computer data bus, applying an address control signal to the multiplexer and passing the address data only to the address bus output as a result thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.