Mechanism for using common code to handle hardware interrupts in multiple processor modes
US5694606A · kind A · utility
53Cited by
18References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1996 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Aug 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt handler may be run in multiple processor modes on a data processing system having a processor for executing instructions and a memory for storing information. The sharing of interrupt handler code across multiple processor modes minimizes the switching between processor modes during the handling of interrupts. The mode in which the interrupt handler executes is dictated by the current processor mode. The indicator of the current processor mode directs the interrupt handler to use information that is appropriate for the current processor mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.