Method of manufacturing Bi-MOS device
US5696006A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1996 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Aug 2, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/009
Abstract
A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.