Method for erasing a common mode current signal and transconductor assembly using such method
US5696457A · kind A · utility
10Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | May 31, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45648
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-voltage transconductor circuit in which the common mode gain of a first transconductor stage is compensated by a second transconductor stage (connected in parallel with the first transconductor stage) which has no differential mode transconductance, and which is connected so that its common mode transconductance offsets the common mode transconductance of the stage. This greatly reduces the common mode current signal at the output, while avoiding the necessity for a current sink at the source of the input transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.