Conditional selection method for reducing power consumption in a circuit
US5696692A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Apr 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing power consumed in a circuit, the circuit having at least a first and a second primary input lead, a plurality of gates, and a plurality of edges, the method includes the steps of determining a set of gates in the circuit coupled to the first primary input lead, the set of gates coupled to a set of edges, determining the 1-controllability of each edge in the set of edges; providing a binary OR tree to the circuit; coupling the set of edges to the binary OR tree; providing an AND gate to the circuit; coupling the AND gate to the binary OR tree and to the first primary input lead; providing a binary AND tree to the circuit; uncoupling the first primary input leads from the set of gates; and coupling the binary AND tree to the AND gate, to the binary OR tree, and to the set of gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.