Method for placing logic functions and cells in a logic design using floor planning by analogy
US5696693A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Mar 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method used by a computer-aided design system for placing logic functions and cells in a floor plan of a very large scale integrated circuit chip. The structure of a set of selected logic functions and cells to be placed is compared to a set of selected logic functions and cells which have previously been placed in the floor plan. If the number of cells and the structure of the sets are analogous, the selected logic functions and cells to be placed are automatically assigned physical positions in the floor plan based on the physical position and structure of the selected logic functions and cells that have already been placed, and on an orientation mode. The orientation mode provides for the reflection of the placement of the selected logic functions and cells about the horizontal axis, the vertical axis, or both the horizontal and vertical axes. The size of the sets of selected logic functions and cells may be arbitrarily large, thereby providing advantages over simple manual placement of logic functions and cells in a floor plan.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.