Digital filter with decimated frequency response
US5696708A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Mar 30, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for changing the frequency of a low-pass Finite Impulse Response (FIR) filter with a fixed frequency clock utilizes a decimation-by-coefficient technique. The decimation-by-coefficient method utilizes a single set of coefficients that are stored in a coefficient Read Only Memory (ROM) (64). Data is input to an elastic buffer (60) with multiplications performed by a multiplication circuit (62). To realize a low frequency filter, all coefficients are utilized in the multiplication operations with sequential multiplies. These are accumulated in register (70), this providing a high precision filter. To increase frequency by a factor of two--to decimate the coefficients by a factor of two, it is only necessary to utilize every other coefficient, such that only a single fixed clock (78) is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.