Power reducing circuit for synchronous semiconductor device
US5696729A · kind A · utility
24Cited by
8References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1994 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Dec 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A power conserving circuit configuration is presented which reduces the power supplied to the input/output pins in the initial input circuit in a synchronous semiconductor device. The circuit reduces the power to the input/output pins in the initial input circuit during the standby mode and/or readout mode, and restores the power to the initial input circuit, when an input signal is entered in an external disabling pin which generates an output disabling signal, which makes the output signal from the input/output pin to be nullified and causes the power to be restored in the synchronous semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.