Bit error measuring apparatus
US5696767A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Sep 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1816
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system measures the positions of bit errors in digital recording devices and displays the physical locations of the bit errors and their distribution in such a manner that they can be grasped visually and intuitively. The system compares a data stream to be measured with a correct data stream and measures the bit errors. The apparatus includes a data stream memory which holds the correct data stream, a comparator, a counter which totals the number of bit errors, a measured bit number counter which totals the measured data stream and determines the boundaries of the logical recording blocks of the recording medium, an error number memory which holds the number of errors in each logical recording block, and an error address memory. The physical locations of bit errors are calculated on the basis of the measured and recorded bit error information for each logical block, and the bit error information is displayed on the physical form of the recording medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.