Two dimensional frame buffer memory interface system and method of operation thereof
US5696947A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Nov 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two dimensional frame buffer memory interface structure is provided. The interface comprises a parallel data bus, a control signal bus, a data cache, and a controller. The parallel data bus transfers a set of pixel data in parallel to the data cache. The control signal bus transfers to the controller a X strobe signal, a Y strobe signal, and a mode signal indicating an interface mode specifying a designated pattern for the pixel data transferred over the parallel data bus. The data cache, controlled by the controller and connected to the parallel data bus, compiles each set of pixel data received over the parallel data bus into the designated pattern of pixels, as indicated by the mode signal. The controller transfers each set of pixel data from the data cache to a two dimensional frame buffer to be stored in the designated pattern at a calculated address, wherein an address in the two dimensional frame buffer is specified by an X address and a Y address and wherein the calculated address for a given set of pixel data is an X address equal to the X address of a previous set of pixel data plus, when a X strobe signal is received for the given set of pixel data, an X increment asso…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.