Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents
US5696956A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Nov 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.