Bus driver
US5698991A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1996 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | Feb 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0292
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bus driver includes a plurality of first to m-th buffer circuits for receiving input of an input signal, a delay circuit for delaying the input signal by a predetermined time period, an n-th buffer circuit for receiving input of a delay signal from the delay circuit, a capacitor for selectively receiving input of a predetermined combination of the output signals of the first to m-th buffer circuits, and an output terminal for outputting a signal composed of the output of the capacitor and the output signal of said n-th buffer circuit. As a result of composition of a plurality of signals output from the capacitive portion and the signal output from the n-th buffer circuit, a plurality of output signals each having different rise time and fall time are output from the output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.