Technique for optimizing the number of IC chips obtainable from a wafer
US5699260A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1995 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | Mar 14, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The yield of good die from wafers is optimized by positioning the first level mask with respect to the wafer in accordance with a calculated alignment relationship based on physical characteristics of the wafer and the size of the die to be formed in the wafer. The calculated alignment relationship establishes the offset between the wafer and the mask which will result in the maximum available die. This offset is calculated by a computer which examines a number of prospective offsets between the center of one of the die and the center of the wafer. The number of available die is calculated for each such offset, and the offset which maximizes the available die from the wafer is determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.