Phase offset cancellation technique for reducing low frequency jitters
US5699387A · kind A · utility
31Cited by
12References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1993 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | Jun 23, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0895
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase locked loop is comprised of a phase-frequency detector for providing to a charge pump up and down pulse signals having pulse widths proportional to phase differences between a pair of signals applied thereto, apparatus for introducing a relative phase difference between a first clock signal and a second signal to provide the pair of signals, the second signal being synchronized with an output signal of the loop, apparatus for providing a third up or down signal to the charge pump offsetting the effect of the introduced phase difference, and apparatus for obtaining a loop control voltage from the charge pump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.