Circular RAM-based first-in/first-out buffer employing interleaved storage locations and cross pointers
US5699530A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1995 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | Oct 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The first-in/first-out (FIFO) buffer includes a first bank of individual storage elements for storing even data and a second bank of individual storage locations for storing odd data. Precharge elements are provided for precharging the even array while data is read from the odd array during one clock cycle and for precharging the odd array while data is read from the even array during a next subsequent clock cycle. Hence, only half of the array is precharged during any one clock cycle. The FIFO buffer is driven by a clock signal having a clock period equal to a minimum precharge time. A 3-input multiplexer is provided with 3 inputs connected, respectively, to an output line of the even array, an output line of the odd array, and an overall input line. In circumstances where data needs to be written to and read from the same storage element in one clock cycle, the multiplexer selects the input line thereby allowing the input data to bypass the storage array for immediate output. The FIFO buffer includes a FIFO read pointer circuit and a FIFO write pointer circuit, each configured as a matrix of individual 2-input AND gates. Each of the gates of the read pointer circuit are connected…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.