Memory system using schottky diodes to reduce load capacitance
US5699541A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1995 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | Mar 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.