Semiconductor integrated circuit which can be tested by an LSI tester having a reduced number of pins
US5701306A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 1995 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Aug 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An LSI (10) to be tested includes a high speed interface (50), a FIFO buffer (16) for temporarily storing data supplied from a high speed interface (50) to an internal circuit (11) of the LSI (10), a selector (24) outputting a selected one of an output of the internal circuit (11) and an output of the FIFO buffer (16) to the high speed interface (50), and a sequencer (17) responding to a test signal (TEST) to control the selector (24) so that the data supplied from the high speed interface (50) to the internal circuit (11) is looped back through the FIFO buffer (16) and the selector (24) to the high speed interface (50). Thus, the LSI (10) including a high speed interface (50) can be tested by use of a high speed LSI tester having a number of pins smaller than the number of all the function terminals of the LSI to be tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.