Method and device for protecting the execution of linear sequences of commands performed by a processor
US5701315A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1995 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Jul 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for detecting errors in a linear sequence of commands executed by a processor and stored in a memory at a predetermined start address, comprises the association of each word in the sequence to a bit of the start address. Before storing each sequence word into the memory, the method determines the value of an unused bit of the word so that the value of the associated bit of the start address will be equal to the result of a predetermined function applied to the bits of the word. When reading a sequence word in said memory, the method compares the result of said function applied to the bits of the word read, with the value of the associated bit of the start address, and transmits an error signal if a difference is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.