Pin and status bus structure for an integrated circuit
US5701421A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1995 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Nov 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
I/O control modules (IOCMs 25-29) include pin/status buses (75-77) which allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Thus, the operation of channels (e.g. 58) can be synchronized with each another. Pin/status buses (75-77) are modular in that they can be extended or alternately segmented to create separate buses carrying different signals. In one embodiment, each end of pin/status bus (75-77) is delineated by a pin control channel (PCCs 51-53). Pin/status buses (75-77) may be used to transfer event information between channels within an IOCM (e.g. IOCM 25), to transfer event information from one IOCM (e.g. 25) to a different IOCM (e.g. 26), and to transfer pin information between integrated circuit pins (31-35) and one or more channels in IOCMs (25-29).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.