Method and apparatus for eliminating latch propagation delays in an alignment unit for use in a fractional bus architecture
US5701447A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 1995 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Jul 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An alignment unit is provided for aligning signals transmitted between a core clock domain and a bus clock domain. The alignment unit includes at least one alignment latch connected along each signal path between the core and bus clock domains. For critical path signal lines, the alignment unit also includes a latch bypass to allow critical signals to bypass the latch in circumstances when the core and bus clock signals are already aligned. The bypass mechanism includes a multiplexer which transmits the critical path signal through a tristate buffer if the clock signals are aligned or through a latch and a tristate buffer if the clock signals are unaligned. By bypassing the latch when the signals are aligned, latch propagation delays are avoided. Method and apparatus embodiments are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.