High-performance non-volatile RAM protected write cache accelerator system employing DMA and data transferring scheme
US5701516A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1996 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Jan 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage system is coupled to a host computer system for the transfer of data between the host and a plurality of data storage devices. The data storage devices are coupled to a plurality of data transfer channels with each data storage channel be coupled to at least a respective one of the data storage devices. Each data transfer channel includes a data buffer and an autonomously operating controller for transferring between the channels data buffer and data storage device. A non-volatile random access storage memory is provided to store cached pages of data. An interface couples the data storage system to the host and through which data is transferred. A reconfigurable data path permits selective data transfer couplings between the data transfers channels, the non-volatile memory, and the interface. A controller directs the configuration of the data path and controls a direct memory access controller for burst transferring data between the interface and the channel data buffers, between the interface and the non-volatile memory and between the non-volatile memory and the channel data buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.