Method for forming a semiconductor device having a floating gate
US5702964A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1995 |
| Grant date | Dec 30, 1997 |
| Priority date | — |
| Expiry date | Oct 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/44
Abstract
A method for forming of a semiconductor device having a transistor with a floating gate includes the steps of forming a first insulating layer and a first conductive layer on a surface of the substrate, patterning the first conductive layer on a cell forming area to form preliminary floating gate electrodes and implanting ions on the cell forming area, forming a second insulating layer on the resulting surface so that the second insulating layer fills a space between the preliminary floating gate electrodes, forming a third insulating layer on the resulting surface, forming a second conductive layer on the third insulating layer, forming a fourth insulating layer on the second conductive layer, forming a gate electrode by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode pattern has a first distance between the gate lines in a portion to be a contact hole, and a second distance between the gate lines is arranged in another portion, the first distance being wider than the second distance, and forming a floating gate electrode by patterning the third insulating layer and the second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.