Fully differential self-biased signal receiver
US5703532A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 1996 |
| Grant date | Dec 30, 1997 |
| Priority date | — |
| Expiry date | Jan 18, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45711
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-biased, fully differential, complementary receiver apparatus and method is presented. The receiver accepts differential inputs that can vary over the full rail-to-rail common mode voltage range. It produces double-ended complementary outputs swinging rail-to-rail useful in signal level conversion and comparator applications. The receiver includes a dual, fully complementary and mirror-symmetrical arrangement of a differential input stage, a biasing stage and an output stage. A self biasing voltage is generated with a balanced voltage divider coupled between the outputs of the biasing stages. This frees both biasing outputs for use as analogous but complementary receiver outputs while providing the receiver with all the advantages of self bias. For small signal differential inputs, the input and biasing stages operate in their linear region useful for amplifier applications. Whereas the circuit is most advantageously implemented using both p-type and n-type CMOS transistors, it can similarly be advantageously implemented with bipolar transistors. Alternate circuit configurations are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.