DRAM for texture mapping
US5703810A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1995 |
| Grant date | Dec 30, 1997 |
| Priority date | — |
| Expiry date | Dec 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latch/mask mechanism that is located between the sense amplifiers of a DRAM and the data bus. The latch/mask mechanism decouples the data bus from the sense amplifiers and permits innovative, time saving functionality during read and write operations. During a write operation, the latch can receive only those byte(s) or a row of bytes to be written. Corresponding mask bits are set to indicate those bytes to be written. Logic in the device transfers only those bytes in the row to be written to the sense amplifiers for writing to memory, leaving the data of remaining bytes in memory intact. Read operations are rendered more efficient by enabling logic, coupled to column select logic, to automatically transfer from the latch the byte selected by the column select logic and the adjacent byte. This time saving feature is particularly useful for computer graphics applications which utilize linear interpolation processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.