Semiconductor memory device having dual boosting circuits to reduce energy required to supply boosting voltages
US5703814A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1996 |
| Grant date | Dec 30, 1997 |
| Priority date | — |
| Expiry date | Jul 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes pairs of bit lines, first circuits which are respectively coupled to the pairs of bit lines and precharge the pairs of bit lines in accordance with a first control signal, sense amplifiers respectively coupled to the pairs of bit lines, and second circuits which are respectively provided between the pairs of bit lines and the sense amplifiers and selectively connect the pairs of bit line to the sense amplifiers in response to a second control signal. A third circuit produces first and second boosted voltages from a power supply voltage and supplies the first and second boosted voltages to the first and second circuits respectively. The first control signal is produced from the first boosted voltage and the second control signal is produced from the second boosted voltage. The first boosted voltage being lower than the second boosted voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.