Memory device with programmable self-refreshing and testing methods therefore
US5703823A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1995 |
| Grant date | Dec 30, 1997 |
| Priority date | — |
| Expiry date | May 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable self-time refresh circuit for a semiconductor memory and methods for programming the self-refresh rate for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.