Vernier delay line interpolator and coarse counter realignment
US5703838A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1996 |
| Grant date | Dec 30, 1997 |
| Priority date | — |
| Expiry date | Feb 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Vernier delay line interpolator provides a precision level smaller than a clock period by delaying a periodic pulse signal in a delay line which has equally time-spaced taps and a total delay that is a harmonic H greater than 1 of the pulse period. The taps of the delay line are latched and decoded to derive the fraction of the pulse period that has passed. When the interpolator is combined with a coarse counter, misalignment between their outputs is prevented by having the coarse counter count both edges of the periodic pulse signal so as to provide redundant bits between the counter and the interpolator. If the redundant bits are not equal, the counter output is corrected before it is combined with the output of the interpolator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.