Multi-channel timing recovery system
US5703905A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 1996 |
| Grant date | Dec 30, 1997 |
| Priority date | — |
| Expiry date | Feb 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An "N" channel receiver system includes "N" A/D converters, one per channel, sampling the data received by their respective channels. The sampling rate of the A/D converters is controlled by a sampling clock signal generated by a timing recovery circuit. One rate of the sampling clock is a function of a timing signal applied to the timing recovery circuit. The system may be configured so that each channel produces N distinct timing signals, corresponding to the data signals received by each one of the N channels. The N distinct timing signals are coupled to a mechanism configured to selectively couple one of the N distinct timing signals to the timing recovery circuit. In a preferred embodiment, the signal-to-noise ratio (SNR) of the N received signals is sensed and the timing signal of the channel having the highest SNR is coupled via the controllable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.