Method of manufacturing a flash EEPROM cell
US5705416A · kind A · utility
9Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1997 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Feb 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
This invention discloses a method of manufacturing a flash EEPROM cell having a split gate structure in which source and drain regions are formed by self align method without using of an additional mask. Problems caused by that length of control gates in each cell are different from each other due to the misalignment between a mask for forming the control gate and a mask for forming source and drain regions are solved since source and drain regions are formed by self align method without using of an additional mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.