Low noise 3V/5V CMOS bias circuit
US5705921A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 1996 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Apr 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/205
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The present invention concerns a circuit for implementing a low noise bias circuit that operates at 3 volts, 5 volts or any desired power supply voltage while avoiding production reconfiguration or post-production configuration. The present invention is implemented by using a current source designed to provide a constant current under differing conditions (e.g., such as a variation in temperature, a variation in power supply, or conditions encountered in a fast transistor process). The present circuit provides a means to adapt to varying conditions. The present circuit generally provides two bias signals that are typically used in a pre-driver circuit implementing NMOS and PMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.