Synthesizable architecture for all-digital minimal jitter frequency synthesizer
US5705945A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 22, 1996 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Jul 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2092
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.