Butted chip array with beveled chips
US5706176A · kind A · utility
7Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1996 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Jul 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an array of butted silicon chips, as would be found in a full-page photosensitive scanner, ink-jet printhead, or LED exposure bar, individual silicon chips forming the array each define a planar bevel near the border of a neighboring chip. The planarity of the bevel avoids damage to the chips when the chips are placed in the chip array assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.