Internal voltage boosting method and circuit for a semiconductor memory device
US5706230A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 1996 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Apr 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal voltage boosting circuit for a semiconductor memory device comprises first and second boosted voltage generators for boosting an internal voltage of said memory device. A voltage level detector is operative to detect the internal voltage. A first logic circuit is operatively connected to the first generator and to the voltage level detector. The logic circuit activates the first generator when (a) the detected voltage falls below a predetermined voltage and (b) the memory device is in an active state. A second logic circuit is operatively connected to the second generator. The second logic circuit activates the second generator when said memory device is in a precharge state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.