Scrambling apparatus and descrambling apparatus
US5706346A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 1994 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Oct 12, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N7/1675
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A scrambling apparatus has at least one of the following processing units: a signal inserting processor for inserting a dummy pattern indicating the quantization width in the compressed video data; a conversion processor for scrambling a signal specifying whether field or frame processing is used; a DCT coefficient conversion processor for scrambling a part of the code defining the DCT coefficient; an intra.sub.-- dc.sub.-- precision conversion processor for scrambling the intra.sub.-- dc.sub.-- precision signal; and an alternate.sub.-- scan conversion processor for scrambling the alternate .sub.-- scan signal. A descrambling apparatus reverses the conversion process on the video data scrambled by the scrambling apparatus to restore the video data to the original unscrambled state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.