Method for a CPU to utilize a parallel instruction execution processing facility for assisting in the processing of the accessed data
US5706489A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1995 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Oct 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for obtaining parallel instruction execution (PIE) for frequently used programming operations, such as database record compression or expansion, cryptographic encoding/decoding, page moving, etc., for which a hardware-assist may be provided. These functions can be performed in parallel with CPU processing by a PIE processing facility (PIE-PF). The method is hardware/microcode based and uses software control in supervisory mode. The preferred embodiment is controlled by privileged subsystem software under an operating system, and does not use I/O channel oriented off-load processing. When the CPU is interrupted during an incomplete parallel operation by the PIE-PF, it is checkpointed in main storage in a manner accessible to the subsystem. The subsystem (after completing a current CPU operation, such as a database record predicate evaluation, can check for the completion of the PIE-PF operation by examining an indicator in a control block in shared storage. Furthermore, if the parallel operation has not completed, the CPU can: a) continue the PIE-PF processing in parallel with other processing in the CPU, b) halt the parallel PIE-PF asynchronous operation and have the CPU d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.