Process for forming field isolation

US5707889A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Ting-Chen Hsu · Taichung, TW
• Laureen H. Parker · Austin, US
• David G. Kolar · Austin, US
• Philip J. Tobin · Austin, US
• Hsing-Huang Tseng · Austin, US
• Lisa K. Garling · Mesa, US
• Vida Ilderem · Phoenix, US

Key dates

• Filing date: May 13, 1996
• Grant date: Jan 13, 1998
• Expiry date: May 13, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.