Dual bus computer architecture utilizing distributed arbitrators and method of using same
US5708784A · kind A · utility
20Cited by
13References
16Claims
0Family size
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Key dates
| Filing date | Feb 20, 1997 |
| Grant date | Jan 13, 1998 |
| Priority date | — |
| Expiry date | Feb 20, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/368
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual bus architecture for a computer system including a number of computer system devices and a number of computer system resources. Each of the computer system devices and computer system resources are coupled by first and second communication busses. First and second bus arbitrators provide bus arbitration functions allowing first and second computer system devices to access first and second computer system resources simultaneously. A method of accessing a number of computer system resources by a number of computer system devices coupled by a dual bus architecture is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.