ATM cell switching system
US5710770A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | Jan 20, 1998 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5682
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted fr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.