Advanced parallel array processor (APAP)

US5710935A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Thomas Norman Barker · Vestal, US
• Clive A. Collins · Poughkeepsie, US
• Michael C. Dapp · Endwell, US
• James Warren Dieffenderfer · Owego, US
• Donald G. Grice · New Paltz, US
• Peter M. Kogge · Endicott, US
• David Christopher Kuchinski · Owego, US
• Billy J. Knowles · Kingston, US
• Donald Michael Lesmeister · Vestal, US
• Richard Ernest Miles · Apalachin, US
• Richard Edward Nier · Apalachin, US
• Eric E. Retter · Austin, US
• Robert Reist Richardson · Vestal, US
• David B. Rolfe · West Hurley, US
• Nicholas Jerome Schoonover · Tioga Center, US
• Vincent John Smoral · Endwell, US
• James Robert Stupp · Endwell, US
• Paul Amba Wilkinson · Apalachin, US

Key dates

• Filing date: Jun 6, 1995
• Grant date: Jan 20, 1998
• Expiry date: Jun 6, 2015

Classification

• Technology area (CPC F): Mechanical Engineering; Lighting; Heating
• CPC primary: F02B2075/027
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.