Memory system and data communications system
US5710944A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1996 |
| Grant date | Jan 20, 1998 |
| Priority date | — |
| Expiry date | Feb 9, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system (3) for storing data messages communicated between a processor unit (13) and a communication module (11), each data message comprising at least one data word, comprises a memory array (4) having a plurality of memory buffers (B0-BM), each buffer for storing a data message, and logic circuitry (24) coupled to the memory array (4). The logic circuitry (24) sets one bit of a data message stored in a memory buffer to a first logic state during a processor unit read access when the processor unit (13) reads a current data message from the memory buffer, and negates the one bit to a second logic state during a communication module write access when the communication module (11) writes a new data message into the memory buffer. When the communication module (11) is to write a new data message to one of the memory buffers, the state of the one bit of the current data message stored in the one memory buffer provides an indication as to whether the new data message will overwrite the current data message, which current data message has not been read by the processor unit (13) or whether the new data message will overwrite the current data message, which current data message h…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.