Semiconductor isolation method
US5712205A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1996 |
| Grant date | Jan 27, 1998 |
| Priority date | — |
| Expiry date | Nov 7, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76237
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a semiconductor isolation method for high density semiconductor(devices of which the isolation pitch is below 0.5 .mu.m. The present invention provides the semiconductor isolation method to improve the isolating characteristics of the semiconductor device by separately performing the isolation process for the area where the isolation pitch is wide from the area where it is narrow. In accordance with the present invention, there is disclosed a semiconductor isolation method including the steps for forming a pad oxide layer and a nitride layer on a semiconductor substrate having an area of relatively narrow isolation pitch and an area of relatively wide isolation pitch, selectively etching the nitride layer and the pad oxide layer on the area of relatively narrow isolation pitch to expose the semiconductor substrate thereunder and forming a trench into a predetermined area of the exposed semiconductor substrate, forming an insulating layer on the resulting structure, removing the insulating layer, whereby the insulating layer remains in the trench, selectively etching the nitride layer on the area of relatively wide isolation pitch, and forming a fiel…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.