Semiconductor device mounted on die pad having central slit pattern and peripheral slit pattern for absorbing
US5712507A · kind A · utility
26Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1996 |
| Grant date | Jan 27, 1998 |
| Priority date | — |
| Expiry date | Jan 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of slits are formed in a die pad of a lead-frame for mounting a semiconductor chip, and are arranged in such a manner as to nearly equalize the length of peripheral sub-areas of the die pad uncovered with the semiconductor chip, thereby effectively absorbing a shrinkage and an elongation due to a difference in thermal expansion coefficient among the die pad, the semiconductor chip and a plastic package hermetically sealing the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.