Shared memory graphics accelerator system
US5712664A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 14, 1993 |
| Grant date | Jan 27, 1998 |
| Priority date | — |
| Expiry date | Oct 14, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.