Error detection system for digital data transmission multiplexing system
US5712862A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1995 |
| Grant date | Jan 27, 1998 |
| Priority date | — |
| Expiry date | Feb 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/14
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
It is an object to efficiently detect and analyze an error occurring on a channel of a digital data transmission multiplexing system with a small circuit scale and a low power consumption. A TU aligner for setting an AU pointer value to zero such that a J1 byte floating in an STM-1 signal is located next to the right one of three H3 bytes in an SOH and changing pointer values (V1 and V2) in each TU channel signal is arranged, and an error which is determined by analyzing each channel signal in the STM-1 signal processed by the aligner and a V5 byte as the POH byte in the signal is detected without demultiplexing the multiplexed STM-1 signal in units of TU channels and which is reported by means of an alarm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.