Synchronized data processing system and image processing system
US5713011A · kind A · utility
35Cited by
11References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1994 |
| Grant date | Jan 27, 1998 |
| Priority date | — |
| Expiry date | Oct 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.