Power semiconductor device
US5714775A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1996 |
| Grant date | Feb 3, 1998 |
| Priority date | — |
| Expiry date | Apr 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/53
Abstract
A p-type emitter layer having a low resistivity is arranged on a bottom surface of an n-type base layer having a high resistivity. A p-type base layer is formed in a top surface of the n-type base layer. Trenches are formed in the p-type base layer and the n-type base layer such that each trench penetrates the p-type base layer and reaches down to a halfway depth in the n-type base layer. Inter-trench regions made of semiconductor are defined between the trenches. An n-type emitter layer having a low resistivity is formed in a surface of the p-type base layer to be in contact with the upper part of each trench. A gate electrode is buried via a gate insulating film in each trench. That side surface of each inter-trench region which faces the gate electrode consists of a {100} plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.